How does binary logic work? Shift registers

teardownit 🛠️ 🔬 ✍️
7 min readMay 10, 2024

--

Sometimes, a microcontroller does not have enough pins to receive signals from buttons or display them on LED indicators, control relays, etc.

Sometimes, one needs to interconnect two digital devices with a single cable, and it would be great to transmit eight, sixteen, or more signals over two to three wires to avoid needing a thick cable.

Or, let’s say we just want to make a lighting effect for a street sign. One does not need a whole computer or a microcontroller for this task. All these cases (and many others) should be designed with shift registers.

As children, many of us had an NES (Nintendo Entertainment System) game console. Its gamepad had 8 buttons: a plus-shaped button for left, right, up, and down, then Select, Start, A, and B. And there were only five wires in the gamepad cable: ground, +5-volt power, and three signal wires. Meaning the state of eight buttons was transmitted over three wires.

In the core of the gamepad is a single CD4021 chip. It is an 8-stage parallel input/serial output shift register. Here is a diagram of its internal logic: the chip has eight inputs for parallel input and outputs from the last three flip-flops.

This should look familiar to our audience: a sequence of synchronous D flip-flops passing the torch of data bits from one to another. Oh, that’s our combination lock from the post on flip-flops!

The CD4021 chip has two operating modes: serial and parallel. In parallel mode, eight flip-flops store information from eight inputs, each individually, regardless of clock pulses.

In serial mode, at the edge of the clock pulse, each subsequent flip-flop receives a data bit from the previous one, and the first flip-flop gets an incoming one from the serial input.

Then, where is the input pin to reset all flip-flops? The answer is there’s none. However, you can pull the serial input low and send eight consecutive clock pulses. If necessary, we can write zeros to all memory cells. Although, in the case of a gamepad, one can do without it.

Simply switch the chip to parallel input mode, and it will save the state of the buttons. Pressed-down buttons correspond to logical zeros; released buttons correspond to logical ones because parallel inputs of the CD4021 in the NES gamepad are pulled by resistors to the power supply positive.

In this case, the DATA wire connected to the output of the eighth flip-flop will contain the state of the button S8 (‘A’). We switch the chip to serial mode, apply clock pulses, and read S7 (‘B’), then S6 (‘Select’), all the way to S1 (‘Right’).

Congratulations! We have read the state of eight buttons via three signal wires (plus two power wires). Then we toggle to parallel mode again, rinse and repeat. This mode toggling is performed lightning fast, and the player will feel like the console responds to button presses instantly.

But what if it’s the other way around, and one doesn’t need to read information from buttons but to write it into cells, for example, by lighting LEDs? Then, a shift register with serial input and parallel output will help.

An example of such a shift register is CD40194. Unlike CD4021, it has not 8, but only 4 digits. Yet it’s got parallel output and input, as well as serial input, with the ability to shift both to the right and left!

Does the CD40194 have a serial output, though? I hear you asking. Of course, it has! Q3 will be the serial output when shifted to the right, and Q0 will be the serial output when shifted to the left.

The CD40194 also has a general reset input. And there are also two mode selection inputs: S0 and S1.

When S0 = 0 and S1 = 0, nothing happens. The chip does not respond to signals other than a general reset, retaining the saved 4 bits of information present at its outputs Q0..Q3.

When S0 = 1 and S1 = 0, a shift to the right occurs at the leading edge of the clock pulse, from Q0 towards Q3. And the value from the left-most serial input is written to Q0.

When S0 = 0 and S1 = 1, a shift to the left occurs at the leading edge of the clock pulse, from Q3 towards Q0. Q3 records the logic level from the right-most serial input.

When S0 = 1 and S1 = 1, logic levels from parallel inputs are read and passed to the output. Moreover, unlike the CD4021, this action requires the leading edge of the clock pulse!

A low level on the master reset input sets all outputs to zero, regardless of clock pulses and the selected operating mode.

Let’s assemble a simple experimental setup to get a complete picture of the CD40194 chip’s operation.

According to the most common scheme, the clock generator is assembled on the U4 NE555 chip. Pulses from its output are sent to the input of CLK U3 CD40194.

Using the SW2 block of 4 microswitches, you can send logical ones and zeros to the parallel inputs of the shift register. Resistors of the set RN1 pull the inputs high, and closed switches connect them to the ground, i.e., pull them low to obtain logical zero.

The reset button SW3 with the pull-up resistor R3 works the same way.

The U1 chip is a four-ship of double-input NAND gates. Both inputs of elements U1C and U1D are connected to each other. This way, the NAND element loses ‘AND’ and turns into the ’N’ (NOT) element — a logical inverter.

Through the inverter U1C, the inverted signal from the left-most output of Q0 goes to the left-shift input, and through U1D, the inverted logic level from the right-most output of Q3 goes to the right-shift input.

Thus, when switching the mode to shift-right, the inverted value of Q3 will be written to Q0; the previous value of Q0 moves to Q1, previous Q1 to Q2, and previous Q2 to Q3.

If the initial state before switching to right shift was all zeros, or if you keep pressing reset in right-shift mode, the register will gradually fill with ones.

When the flow of ones reaches the end (Q3), the value one will be inverted, and the register will start filling itself with zeros. And when a zero reaches Q3, the cycle will repeat.

The same process will only happen in the opposite direction when switching to the shift left mode.

And in parallel input mode, the register will read the position of the microswitches whenever a clock pulse arrives.

To visually indicate the operating modes of the CD40194 shift register, we’ve assembled a two-digit pulse counter on two flip-flops of the U2 CD4027. They operate as a frequency divider and cycle between four states: 00 → 01 → 10 → 11.

The state of the CD40194’s outputs is indicated by four red LEDs. The status of its control inputs is indicated by two blue LEDs (one of which had to be replaced with a green one because the blue one was faulty). The LEDs are turned on using S9014 transistors.

Pulses for a two-bit binary counter that switches shift register modes are generated by an RS flip-flop on two NAND gates, U1A and U2A. It switches when the button SW1 is pressed. We’ve talked about the operation of such a circuit in the post about flip-flops.

The video shows this experimental circuit board in operation.

--

--